(a). Field of the Invention
The present invention relates to a data processing circuit having a waiting mode and, more particularly, to a data processing circuit operating in an active mode and a waiting mode based on the mode switching signal.
(b). Description of the Related Art
Some data processing circuits such as a DRAM are operated for data processing in an active mode and for maintaining the data stored therein in a waiting mode. A circuit configuration of a DRAM will be described below with reference to FIG. 1 as an example of such a data processing circuit.
The DRAM, generally denoted by numeral 100, includes a data processing section 101, a power source section 102 and a compensating capacitor 103 which are connected through a source line 104. The power source section 102 has a feed line 111, a pMOSFET 112 and a differential amplifier 113 for supplying a power source having an operational voltage of VINT through the source line 104.
More specifically, in the power source section 102, the feed line 111 is supplied with a power source having an external voltage of VEXT, whereas the inverting input of the differential amplifier 113 is applied with a reference voltage VREE The pMOSFET 112 has a source connected to the feed line 111 and a drain connected to the source line.
The gate of the pMOSFET 112 is connected to the output terminal of the differential amplifier 113, and the source line 104 is connected to the non-inverting input of the differential amplifier 113 for feed-back. In this configuration, the external voltage VEXT is converted by the power source section 102 into the operational voltage VINT, which is equal to the reference voltage VREF and fed through the source line 104.
The processing section 101 includes a memory cell array, a decoder block, a sense amplifier block etc., which are implemented by CMOSFETs and other transistors. The processing section 101 conducts for read/write operation of data in the memory cell array while consuming electric power having the operational voltage VINT.
The compensating capacitor 103 has a specified capacitance, and alleviates the fluctuations of the operational voltage VINT on the source line 104 due to the charge and discharge of the capacitor 103. These circuit components 101 to 104 are generally integrated into a single chip LSI, and may be called a single chip DRAM.
In the DRAM having such a configuration, the power source section 102 generates the operational voltage VINT, which allows the processing section 101 to operate for write/read processing. The compensating capacitor 103 alleviating the voltage fluctuations of the operational voltage VINT allows the data processing section 101 to operate in a stable state.
The DRAM 100 as described above is generally used as an electronic component in a computer system, for example. It is known that some of the DRAMs have modes including an active mode, an off mode and a waiting mode (sleep mode or inactive mode). The data processing section 101 operates for read/write processing to consume electric power if the DRAM 100 resides in the active mode, whereas the processing section 101 does not operate for read/write processing if the DRAM 100 resides in the off mode or the waiting mode.
If the operational voltage supplied to the data processing section 101 is made completely off, the data stored in the processing section 101 is lost. This mode is called an off mode wherein the supply of power source is completely stopped for allowing the stored data to be lost in the data processing section 101.
In a waiting mode, the data processing section 101 does not operate for read/write processing and maintains the data already stored therein, thereby dissipating only a small amount of electric power. The power source section 102 supplies the operational voltage to the processing circuit in this mode to allow the processing circuit to maintain the data.
Along with the increase in the integration density of the DRAM or LSI, the MOSFETs have lower threshold voltages which cause the increase of the leakage current. Thus, the power source dissipated by the data processing section in the waiting mode increases and is not negligible in the large integrated circuit.
Patent Publication JP-A-7-254685 describes a data processing circuit for lowering the power dissipation during the waiting mode, wherein the power source section generates a lower waiting voltage in the waiting mode, and the threshold voltage in the processing section is also raised by controlling the substrate voltage in the waiting mode.
In the described circuit, the lower waiting voltage supplied to the data processing section is raised up to the higher operational voltage during the transient period from the waiting mode to the operational mode. In this period, the increase of the line voltage on the source line by the power source section is mainly used for charging the compensating capacitor, which is maintained at the lower waiting voltage in the previous waiting mode. Thus, the higher operational voltage is not supplied to the processing section in a short time during the transient period, which fact delays the response of the processing section just after shifting of the mode from the waiting mode to the operational mode.